High peak current density resonant tunneling diode

ABSTRACT

A resonant tunneling diode is produced in a gallium arsenide material system formed with barrier layers of AlGaAs with a quantum well layer of low band-gap material between them. The material of the well is selected to adjust the second energy level to the edge of the conduction band in GaAs, with a preferred quantum well layer formed of InGaAs. The resonant tunneling diode structure is grown by a metal organic chemical vapor deposition process on the surface of the nominally exact (100) GaAs substrate. Layers of doped GaAs may be formed on either side of the multilayer resonant tunneling diode structure, and spacer layers of GaAs may also be provided on either side of the barrier layers to reduce the intrinsic capacitance of the structure.

[0001] This application claims the benefit of U.S. provisionalapplication No. 60/020,141, filed Jun. 21, 1996.

FIELD OF THE INVENTION

[0002] This invention pertains generally to the field of semiconductordevices and more particularly to resonant tunneling diodes.

BACKGROUND OF THE INVENTION

[0003] Resonant tunneling diodes comprise semiconductor structureshaving two large band-gap barrier layers with a single low band-gapquantum well between them. Collector 30 and emitter 31 contact regionsare provided in the semiconductor structure to provide collection andsupply of electrons as illustrated in the simplified band diagram ofFIG. 1. The thicknesses of barrier layers 34 and 35 and the thickness ofthe quantum well 36 between them, and the composition of thesestructures, are chosen so that quantum effects create a single resonantenergy level 37 slightly above the emitter conduction band edge 38. Asthe emitter 31 is negatively biased, the two bands will come intoalignment at a peak voltage V_(p), as illustrated in FIG. 2, andelectrons will tunnel through to the collector region 30 where they arecollected. As the negative bias is increased still further, the emitterconduction band 38 rises above the resonant energy level 37, asillustrated in FIG. 3, drastically reducing the tunneling current. Theresult is a negative resistance region that creates the utility of theresonant tunneling diode (RTD). As the emitter bias is increased stillfurther, current will rise again as electrons are emitted over thebarrier. FIG. 4 shows a typical current-voltage relationship curve 40for a typical RTD.

[0004] The high speed voltage transition occurs when the RTD is switchedfrom the stable point “a” in FIG. 4 to the stable point “b”. The voltageswing is maximized by making the voltage V_(p) low and the voltage V_(v)high. Switching speed is maximized by making the peak current I_(p) aslarge as possible for a given conduction area. The valley current at thevoltage V_(v) is of great significance for high-speed applications, andshould be as low as possible to maximize the current available to chargethe load capacitance thus reducing the switching time.

[0005] It is desirable that RTDs be highly reliable and stable over timeand with temperature changes, and have typical performancecharacteristics that include voltage swings of one to two volts, peakcurrent densities of 100 to 200 kA/cm², peak currents of 10 to 20 mA,peak voltages of 1 volt, peak to valley current ratios of at least 3,and a rise time of less than 2 picoseconds. Such characteristics havebeen achieved previously in devices made of pseudomorphic AlAs/InAs/AlAsquantum wells fed by lattice-matched InGaAs contact layers, and grown onInP by molecular beam epitaxy. However, the InP material system is notwell suited for practical applications, and the technology is immature.GaAs would be ideal, but GaAs/AlAs RTDs cannot reach the performances ofInP-based devices.

SUMMARY OF THE INVENTION

[0006] The resonant tunneling diode (RTD) of the present inventioncombines all of the desirable characteristics for such a diode in asingle device which can be produced in a gallium arsenide materialsystem using the processing techniques compatible with large scaleproduction, particularly metal organic chemical vapor deposition(MOCVD). The device is capable of peak current densities in excess of300 kA/cm² at relatively low peak voltages in the range of 1 volt.Switching times in the range of 1 picosecond can be obtained.

[0007] The multilayer RTD structure preferably is formed of barrierlayers of AlGaAs with a quantum well layer formed of low band-gapmaterial between them. The material of the well is selected to adjustthe second energy level to, i.e., at or slightly above, the edge of theconduction band in GaAs. A preferred material for the quantum well layeris InGaAs. The RTD structure is grown by an MOCVD process on the surfaceof a nominally exact (100) GaAs substrate. To complete the device,layers of doped GaAs may similarly be formed on either side of themultilayer RTD structure. Spacer layers of GaAs may also be provided aspart of the RTD structure on either side of the barrier layers to reducethe intrinsic capacitance of the structure.

[0008] It has been found that in the present invention a structure grownby the MOCVD process on the exact (100) GaAs substrate will producesmooth interfaces between the various layers, including the strainedlayer quantum well structure, to allow the achievement of high currentdensity and other desirable characteristics at conventional operatingtemperatures (e.g., 300 K). The resulting structure provides resonanttunneling through the second energy level in a strained-layerquantum-well. The growth of strained-layer InGaAs quantum wellstructures using exact on-orientation substrates produces distinctlayers with relatively abrupt transitions at interfaces, significantlyimproving the smoothness of the interfaces and consequent deviceperformance over devices which are grown off-orientation. Specifically,rough interfaces cause carrier scattering which significantly increasesthe valley current and thus makes the device impractical. By smoothingthe interfaces, high peak-to-valley ratios can thus be obtained.

[0009] Further objects, features and advantages of the invention will beapparent from the following detailed description when taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings:

[0011]FIG. 1 is a simplified band diagram of a typical resonanttunneling diode (RTD) structure.

[0012]FIG. 2 is a band diagram as in FIG. 1 illustrating negative biasof the emitter.

[0013]FIG. 3 is a band diagram as in FIG. 2 with further negative biasof the emitter.

[0014]FIG. 4 is a typical current-voltage relationship curve for atypical RTD.

[0015]FIG. 5 is a simplified band diagram for the RTD of the presentinvention.

[0016]FIG. 6 is a simplified schematic view of the multilayer structureof an embodiment of an RTD in accordance with the present invention.

[0017]FIG. 7 is a cross-sectional view of an RTD semiconductor deviceformed in accordance with the present invention.

[0018]FIG. 8 are calculated peak current density (stars) and peakvoltage (blank circles) as a function of well width for the RTDembodiment of FIG. 6.

[0019]FIG. 9 is a measured current-voltage curve for a 6*6 μm² RTDdevice in accordance with the present invention operating at roomtemperature.

DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention achieves all of the desirablecharacteristics for an RTD in a device structure in the GaAs materialsystem. GaAs is a preferred material because it is less expensive thanInP, its technology is the most mature of all III-V material systems,and it provides the possibility of integration with other high-speeddevices. A conduction band diagram for an RTD quantum well of apreferred resonant tunneling diode in accordance with the presentinvention is illustrated in simplified form in FIG. 5, illustrating aGaAs emitter region 50, a first barrier layer 51 and a second barrierlayer 52, both formed of AlGaAs, a quantum well layer 53 between thelayers 51 and 52, which is formed of InGaAs, and a GaAs collector layer55 adjacent to the barrier layer 52. In such a multilayer RTD structurethe second level band 56 is slightly above the emitter conduction bandedge 57. The first level band is illustrated at 58 in FIG. 5. The secondlevel is preferably just at or, as a practical matter, slightly abovethe conduction band edge because peak voltage for the device increasesrapidly as the second level is raised further above the conduction bandedge.

[0021] A schematic view of a practical RTD multilayer structure 60 grownby metal organic chemical vapor deposition (MOCVD) is given in FIG. 6.In this device, n-type gallium arsenide (GaAs) is used as a substrate61. A suitable dopant is silicon. On this substrate is grown a layer ofGaAs 62, followed by the multilayer RTD structure 60 formed of the GaAsspacer layer 55, the barrier layer 52, the quantum well layer 53, thebarrier layer 51, and the GaAs intrinsic layer 50, and then followed bya further layer 63 of n-doped GaAs. A cross-sectional view of thephysical arrangement of the device is shown in FIG. 7. The RTD structure60 is preferably grown on the exact-orientation (100) GaAs substrate 61.An insulating layer of silicon dioxide (SiO₂) 72 is formed over thesubstrate 61 and the structure 60 is grown on the substrate, with anopening provided in the insulating layer 72 over an already depositedGe—Au/Ge—Ni—Au contact 73. A conducting layer 75 of, e.g., Ti—Pt—Au isdeposited over the SiO₂ insulating layer 72 and forms an electricalconnection to a contact 73 to form one externally accessible terminal ofthe device.

[0022] By taking advantage of resonant tunneling through the secondenergy level of a deep quantum well in a strained-layer structure, thisRTD structure provides two times higher peak current densities (PCD's)than conventional GaAs-based resonant tunneling diodes (RTD's) and morethan 3 times higher PCD values than those typical of MOCVD-grown RTD's.PCD values higher than 300 kA/cm², peak voltages as low as 1.2 volts,and peak-to-valley current ratios (PVR's) of 3:1 at 300 K are obtainedfrom the structures of FIGS. 7 with, e.g., 14 Å-thick Al_(0.8)Ga_(0.2)Asbarriers 51 and 52 and a 57 Å-thick In_(0.3)Ga_(0.7)As well 53. Thethickness of the various layers can be measured by transmission electronmicroscopy (TEM).

[0023] The GaAs-based RTDs of the present invention have practicaladvantages over GaSb- and InP-based structures due to the maturity ofgrowth and material processing techniques for GaAs, as well as thepossibility of integration of these RTD's with other high-speed devices.The need for relatively high current density, which is basically thecrucial figure of merit for high-speed RTD switching applications, hasbeen a major drawback for previous GaAs-based RTD's. As reported in T.P. E. Broekaert, et al., Appl. Phys. Lett., 53 (16), pp. 1545-1547,October 1988, the peak current density associated with the secondresonant energy level of an RTD is almost 10 times greater than the oneresulting from the first energy level for the same structure, but thislevel has, however, been attainable only at high peak voltages (≈4volts). In the present invention, by using a low-bandgap material,In_(0.3)Ga_(0.7)As, for the well, the second resonant energy level iswell-adjusted to the edge of the conduction band of GaAs, and thusprovides a relatively low peak voltage. FIG. 8 shows calculated datademonstrating that, for the structure of FIGS. 6 and 7, (anIn_(0.3)Ga_(0.7)As well, 14 Å-thick barriers, and a 300 Å-thick spacerlayer), very high PCD values together with a relatively low peak voltageare obtained, while the well thickness stays below the critical valuefor In_(0.3)Ga_(0.7)As grown on GaAs substrate (≈100 Å).

[0024]FIG. 9 shows the measured I-V curve for a 6*6 μm² device as inFIG. 7. Circuit simulations show that this device, if fabricated withminimal parasitic capacitance, can switch 1 volt in less than 3 ps.Optimized spacer layer structures that minimize intrinsic capacitancecan be utilized to reduce the switching time by a factor of two or more,resulting in subpicosecond switching speed. The relatively goodpeak-to-valley current ratio shown in FIG. 9 results from the use of adeep quantum well, good ohmic contacts made by a 2-step process (i.e.,as shown in FIG. 7), and the growth on an exact-orientation (100)-GaAssubstrate 61, which results in smooth interfaces between thestrained-layer quantum well 53 and the barriers 51 and 52.

[0025] The following is an illustrative example of a fabrication processin accordance with the invention. The fabrication process consists oftwo major steps: structure growth and device fabrication.

[0026] Material growth is carried out by the Metal Organic ChemicalVapor Deposition (MOCVD) technique, and the quality of the grownstructures can be examined by transmission electron microscopy (TEM). Byrunning TEM on several test structures, the growth rates for variouslayers are very well calibrated (at the level of a few i). The processis composed of various steps to fabricate proper contacts for emitterand collector sides, and to etch mesas to form isolated devices. Due tothe crucial effect of series resistance on the negative differentialresistance of RTD's, a two-step process is used to make a low-resistanceohmic contact on top of the mesa (emitter side). Metal contacts aredeposited by e-beam metal deposition and patterned by the lift-offtechnique. The structure may also be grown on a semi-insulating GaAssubstrate in accordance with conventional planar processing techniques,in which case all contacts are formed on the same side of the substrate.

[0027] A total of three different masks are used throughout thefabrication process; the most precise alignment needed in the process isthe alignment of windows in an SiO₂ isolation layer with the top metalcontacts. The fabrication process is explained in greater detail below.

[0028] The RTD structure is grown using low-pressure (50 mbar)metalorganic chemical vapor deposition (LP-MOCVD) in an Aixtron A-200system, at a growth temperature of 700° C. The metalorganic precursorsare trimethylgallium, trimethylaluminum, and trimethylindium. The groupV source is arsine with silane used as an n-type dopant. Prior to growthof the RTD structure, the solid composition (x) of Al_(x)Ga_(1−x)As ismeasured using x-ray diffraction, as a function of the aluminumgas-phase mole-fraction. Growth rates are obtained from film-thicknessmeasurements using scanning electron microscopy. Similarly, the solidcomposition (y) of In_(y)Ga_(1−y)As is determined from x-ray diffractionrocking curve measurements on thick (relaxed) layers.

[0029] To improve the quantum-well interfacial morphology, RTDstructures are grown on nominally exact (100), 0° to ±0.5°, andpreferably ±0.1°, GaAs substrates. Such a substrate orientation isselected because recent studies of strained-layer InGaAs quantum-wellstructures, via atomic force microscopy (AFM) and low-temperaturephotoluminescence, indicate that growth using exact on-orientationsubstrates significantly improves the interfacial structure byeliminating step-bunching. By contrast, the growth of strained-layerInGaAs quantum wells on misoriented substrates will generally result inincreased surface roughness and broadening of low-temperaturephotoluminescence. After growth of the RTD structure, the thicknesses ofthe layers are confirmed using high-resolution TEM lattice imaging. TheTEMs of In_(0.3)Ga_(0.7)As/Al_(0.8)Ga_(0.2)As/GaAs structures show aclear image of distinct layers with relatively abrupt transitions atinterfaces. From a high-resolution TEM lattice image, it is possible toestimate the thicknesses of the first barrier 52 (from the bottom), well53, and second barrier 51 as being 14.5 Å, 57 Å, and 13 Å, respectively,which estimates are in good agreement with the target values. Aschematic view of the grown structure 60 in FIG. 6 includes (from bottomto top): a 300 Å spacer layer 55 to reduce the intrinsic capacitance ofthe device, a 14 Å Al_(0.8)Ga_(0.2)As barrier layer 52, a 57 ÅIn_(0.3)Ga_(0.7)As well 53, the second barrier layer 51, and a 100 Ålayer of intrinsic GaAs to separate the structure from the doped toplayer 63.

[0030] The device fabrication starts with the deposition of the topmetal contact using e-beam metal deposition. In order to make a goodohmic contact, a sequence of various metal layers are used, such asGe—Au/Ge—Ni—Au. The deposited metal is patterned to 3×3 μm² squares,separated by 1 mm from each other. Then, using chemical etching, mesasof different sizes (from 5×5 μm² to 8×8 μm²) are etched around contacts.After covering the whole wafer with a 1000 Å-thick SiO₂ film 72 as anisolation layer, 3×3 μm² windows are opened on top of the buriedcontacts. Then, the second layer of metal, composed of Ti—Pt—Au layers,is deposited on the wafer. In order to facilitate cleaving the waferinto devices, the wafer is thinned to 150 μm by mechanical lapping.After depositing the back contact 76 (Ge—Au/Ge—Ni—Au), the contacts arealloyed by rapid thermal annealing in order not to damage the structure(at 400° C. for 30 seconds). The last step is to cleave the wafer intodevices.

[0031] The major fabrication process steps are summarized below, withfurther details for steps 4-11:

[0032] 1. System calibration.

[0033] 2. Wafer preparation (if necessary).

[0034] 3. MOCVD device growth.

[0035] 4. Patterning top contact by lift-off method;

[0036] a) Using mask 2 and negative photoresist to pattern 3 μm by 3 μmcontacts.

[0037] b) Metal evaporation Ge—Au/Ge—Ni—Au.

[0038] c) Removing extra metal.

[0039] 5. Chemical etching to isolate devices:

[0040] a) Photolithography using mask 1.

[0041] b) Chemical etching for a thickness of greater than 1 μm.

[0042] 6. SiO₂ deposition by PE-CVD.

[0043] 7. Patterning SiO₂ to open 3 μm by 3 μm windows, using mask 2.

[0044] 8. Top contact deposition and patterning by lift-off (mask 3)Ti—Pt—Au.

[0045] 9. Wafer thinning.

[0046] 10. Bottom contact deposition Ge—Au/Ge—Ni—Au.

[0047] 11. Making ohmic contacts by annealing @400C. for 30 seconds.

[0048] 12. Cleaving.

[0049] Step 4-a:

[0050] In order to be able to pattern metal contacts on wafer throughthe lift-off technique, the thickness of photoresist must be greaterthan the thickness of deposited metal. Therefore, for this step ShipleyAZ 1375 negative photoresist is used.

[0051] Spinning: 4500 RPM for 30 seconds

[0052] Prebake: 30 min. @90° C.

[0053] Exposure time: 45 sec. using mask aligner Karl Suss MJB3 (mask2).

[0054] Developing: MF 321 for 1 min.

[0055] Postbake: 30 min. @120° C.

[0056] Step 4-b:

[0057] The metal is deposited on top of the patterned photoresist byE-beam metal deposition (CHA Industries) at a pressure below 10⁻⁶ Torr.

[0058] Ge: 200 Å

[0059] Au/Ge: 800 Å

[0060] Ni: 300 Å

[0061] Au: 1000 Å

[0062] Step 4-c:

[0063] By placing the wafer in acetone and using ultrasound agitation,the extra metal from the surface of wafer is lifted (2 min.).

[0064] Step 5-a:

[0065] Shipley AZ 1805 negative photoresist is used as the mask for mesadefinition during the wet etching process. Mask 1 is used to pattern thephotoresist.

[0066] Spinning: 5000 RPM for 30 seconds

[0067] Prebake: 30 min. @90° C.

[0068] Exposure time: 2.7 sec. (mask 1).

[0069] Developing: MF 321 for 45 sec.

[0070] Postbake: 30 min. @120° C.

[0071] Step 5-b:

[0072] Isolated mesa structures are formed by the wet etching processusing H₃PO₄/H₂O₂/H₂O (5:1:1) solution. The mesas are etched as high as 1μm at a rate of 4000 Å/min at 9° C.

[0073] Step 6:

[0074] Through Plasma Enhanced Chemical Vapor Deposition (PE-CVD)(Waf'r/Batch Plasma-Therm 70 series system), a 1000 Å-thick layer ofSiO₂ is deposited on the structures.

[0075] Pressure: 900 mTorr.

[0076] Temperature: 250° C.

[0077] Step 7:

[0078] In order to open windows in the SiO₂ layer, Shipley AZ 1813negative photoresist is used which is thick enough to cover the mesas,and forms a planar surface proper for photolithography.

[0079] Spinning: 4000 RPM for 30 seconds

[0080] Prebake: 30 min. @90° C.

[0081] Exposure time: 7 sec (mask 2).

[0082] Developing: MF 321 for 1 min.

[0083] Postbake: 30 min @120° C.

[0084] Step 8:

[0085] The second layer of top metal was deposited by e-beam metaldeposition and patterned by lift-off (mask 3).

[0086] Ti: 500 Å

[0087] Pt: 600 Å

[0088] Au: 1000 Å

[0089] Step 9:

[0090] In order to facilitate cleaving the wafer into devices, it isthinned to 150 μm by mechanical lapping (LOGITECH PM2A machine and 3 μmAluminum Oxide powder).

[0091] Step 10:

[0092] Deposition of bottom contact: The same as step 4-b.

[0093] Ge: 200 Å

[0094] Au/Ge: 1000 Å

[0095] Ni: 300 Å

[0096] Au: 3000 Å

[0097] Step 11:

[0098] By Rapid Thermal Annealing (RTA), the contacts are alloyed at400° C. for 30 seconds which is short enough not to damage the grownstructure.

[0099] It is understood that the present invention is not limited to theembodiments disclosed herein, but encompasses all such forms thereofthat come within the scope of the following claims.

What is claimed is:
 1. A resonant tunneling diode comprising: (a) asubstrate of (100) GaAs; (b) a multilayer resonant tunneling diodestructure grown on the (100) GaAs substrate, the resonant tunnelingdiode structure comprising a quantum well layer of low band-gap materialbetween barrier layers of AlGaAs, and wherein the material of thequantum well layer is selected such that the second energy level of thequantum well layer is at or slightly above the conduction band edge inGaAs, the quantum well layer grown to be a strained layer with smoothinterfaces with the barrier layers.
 2. The resonant tunneling diodedevice of claim 1 wherein the quantum well layer comprises InGaAs. 3.The resonant tunneling diode device of claim 2 wherein the barrierlayers are composed of Al_(0.8)Ga_(0.2)As, and the quantum well layer isformed of In_(0.3)Ga_(0.7)As.
 4. The resonant tunneling diode device ofclaim 3 wherein the barrier layers are about 14 Å thick and the quantumwell layer is about 57 Å thick.
 5. The resonant tunneling diode deviceof claim 2 including a spacer layer of intrinsic GaAs adjacent to eachbarrier layer.
 6. The resonant tunneling diode device of claim 5 furtherincluding a layer of n-doped GaAs adjacent to each GaAs intrinsic layer.7. The resonant tunneling diode device of claim 6 wherein the substrateis doped GaAs and the resonant tunneling diode structure is isolated ona mesa with a doped GaAs layer at the top of the mesa and furtherincluding an insulating layer over the exposed surfaces of the substrateand the mesa and a contact formed through the insulating layer to thedoped GaAs layer, and a contact on the doped GaAs substrate opposite themesa.
 8. The resonant tunneling diode device of claim 1 wherein theresonant tunneling diode structure is grown on a nominally exact (100)±0.5° GaAs substrate.
 9. The resonant tunneling diode device of claim 1wherein the resonant tunneling diode structure is grown on a nominallyexact (100) ±0.1° GaAs substrate.
 10. The resonant tunneling diodedevice of claim 1 wherein the resonant tunneling diode structure isgrown on the GaAs substrate by metal organic chemical vapor deposition.11. A resonant tunneling diode comprising: (a) a substrate of (100)GaAs; (b) a multilayer resonant tunneling diode structure grown on the(100) GaAs substrate, the resonant tunneling diode structure comprisinga quantum well layer of InGaAs between barrier layers of AlGaAs, aspacer layer of intrinsic GaAs adjacent to each barrier layer, and alayer of n-doped GaAs adjacent to each GaAs intrinsic layer, wherein thesecond energy level of the quantum well layer is at or slightly abovethe conduction band edge in GaAs, the quantum well layer grown by metalorganic chemical vapor deposition to be a strained layer with smoothinterfaces with the barrier layers.
 12. The resonant tunneling diodedevice of claim 11 wherein the barrier layers are composed ofAl_(0.8)Ga_(0.2)As, and the quantum well layer is formed ofIn_(0.3)Ga_(0.7)As.
 13. The resonant tunneling diode device of claim 12wherein the barrier layers are about 14 Å thick and the quantum welllayer is about 57 Å thick.
 14. The resonant tunneling diode device ofclaim 11 wherein the substrate is doped GaAs and the resonant tunnelingdiode structure is isolated on a mesa with a doped GaAs layer at the topof the mesa and further including an insulating layer over the exposedsurfaces of the substrate and the mesa and a contact formed through theinsulating layer to the doped GaAs layer and a contact on the doped GaAssubstrate opposite the mesa.
 15. The resonant tunneling diode device ofclaim 11 wherein the resonant tunneling diode structure is grown on anominally exact (100) ±0.5° GaAs substrate.
 16. The resonant tunnelingdiode device of claim 11 wherein the resonant tunneling diode structureis grown on a nominally exact (100) ±0.1° GaAs doped substrate.
 17. Amethod of making a resonant tunneling diode comprising the steps of: (a)providing a substrate of nominally exact (100) GaAs; (b) growing on thesubstrate by metal organic chemical vapor deposition successive layerscomprising at least a barrier layer of AlGaAs, a strained quantum welllayer of low band-gap material, and a barrier layer of AlGaAs, thequantum well layer grown with smooth interfaces with the barrier layerswith the second energy level of the quantum well layer at or slightlyabove the conduction band edge in GaAs.
 18. The method of claim 17wherein the quantum well layer material is InGaAs.
 19. The method ofclaim 15 wherein the barrier layers are formed to be composed ofAl_(0.8)Ga_(0.2)As, and the quantum well layer is formed to be composedof In_(0.3)Ga_(0.7)As.
 20. The method of claim 17 further includinggrowing by metal organic chemical vapor deposition a spacer layer ofintrinsic GaAs adjacent to each barrier layer.
 21. The method of claim20 further including growing by metal organic chemical vapor depositiona layer of n-doped GaAs adjacent to each GaAs intrinsic layer.
 22. Themethod of claim 21 wherein the substate is doped GaAs and includingisolating the resonant tunneling diode structure on a mesa with a dopedGaAs layer at the top of the mesa and further including forming aninsulating layer over the exposed surfaces of the substrate and the mesaand forming a contact through the insulating layer to the doped GaAslayer and forming a contact on the doped GaAs substrate opposite themesa.
 23. The method of claim 17 wherein the substrate is nominallyexact (100) ±0.5° GaAs.
 24. The method of claim 17 wherein the substrateis nominally exact (100) ±0.1° GaAs.